Efficient Hardware Architectures for Data Driven Time Frequency Algorithm
Abstract
Data-driven methods such as Empirical Mode Decomposition (EMD), Multivariate Empirical Mode Decomposition (MEMD), and Variational Mode Decomposition (VMD) have proven to be extremely useful in diverse fields for decomposition and time-frequency analysis of non-stationary data. Moreover, multivariate, or multichannel data have become ubiquitous in many modern scientific and engineering applications (such as biomedical engineering) due to recent advances in sensor and computing technology. Processing these datasets is challenging because of their large size and multidimensional nature, requiring specialized algorithms and efficient hardware designs for online and real-time processing.
EMD and MEMD, in their original formulation, both works collectively on a batch data and hence are not suitable for online applications that require continuous real-time data processing capability. Few Field Programmable Gate Array (FPGA) based hardware designs for EMD computations have emerged in recent years, yet none have found considerable success in practical applications. The main reason for this issue is that existing designs mostly use linear interpolation instead of well-established Cubic Spline Interpolation (CSI) for the sifting process within EMD. Although fewer hardware resources and lower execution time are reported, but the accuracy of EMD decomposition is significantly compromised due to usage of linear interpolation. Moreover, MEMD is another data-driven method that extends the functionality of the standard EMD algorithm to multichannel or multivariate datasets. MEMD algorithm has found widespread applications spanning different fields which are related and not limited to engineering. EMD and MEMD required recursive operation while an advanced data driven algorithm named as VMD is a non-recursive and adaptive data-driven method to decomposed real value signal into a distinct number of finite band-limited IMFs. VMD is based on a variational approach, so the Alternate Direction Method of Multipliers (ADMM) techniques has been used in the VMD algorithm. At present, no parallel FPGA based hardware design for both algorithm MEMD and VMD is available for its online and real-time processing. In this thesis, three parallel architectures for data-driven algorithms are presented; i) FPGA-based real-time implementation of online EMD with fixed-point architecture ii) FPGA-based hardware architecture of a popular multi-scale and multivariate signal processing algorithm, termed as Multivariate Empirical Mode Decomposition (MEMD) iii) FPGA-based architecture for VMD. The proposed FPGA-based architectures for EMD and MEMD work on fixed-point data formats, thereby alleviating the main source of error in existing EMD based architectures. The proposed designs implement computationally extensive CSI and accommodating linear interpolation within the sifting process in EMD and MEMD, which further improves its accuracy. The proposed pipeline designs ensure that despite implementing computationally expensive EMD related tasks, the proposed architecture exhibits minimum execution time and high throughput when compared with existing EMD and MEMD architectures. The proposed EMD architecture achieved maximum operating frequency of 46.44MHz with overall data throughput of 620Mbps. Moreover, the proposed MEMD design attained even higher throughput of 1302 Mbps and achieved clock rate of 31MHz. The proposed VMD architecture has achieved maximum operating frequency of 50MHz with batch processing. Finally, a comprehensive performance of each architecture has been verified with the decomposition of synthetic and real-world biological signals. The results show that the proposed method achieved higher throughput and lesser computational time while keeping the accuracy high. The proposed system has a potential to embed with online and real-time data driven systems.
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